1. Field of the Invention
The present invention relates to error correction, and more particularly, to an error correction circuit, an error correction method, and a semiconductor memory device including the error correction circuit.
This application claims the benefit of Korean Patent Application No. 10-2006-0080854, filed on Aug. 25, 2006 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
2. Description of the Related Art
With the increase in memory capacity of a semiconductor memory device, an error correction circuit which can recover an error in a memory cell is required. Conventional error correction circuits may be divided into circuits using a redundant memory cell and circuit using error checking and correction (ECC).
A semiconductor memory device including an error correction circuit using a redundant memory cell includes normal memory cells and redundant memory cells and replaces a defective memory cell having an error with a redundant memory cell when writing and/or reading data. The error correction circuit using a redundant memory cell is usually used for dynamic random access memory (DRAM).
A semiconductor memory device including an error correction circuit using ECC generates and stores redundant data (referred to as parity data or syndrome data) and detects and corrects errors occurring in data bits using redundant data. The error correction circuit using ECC is usually used for read-only memory (ROM) and especially used very often for flash memory including electrically erasable and programmable ROM (EEPROM) cells.
FIG. 1 is a schematic block diagram of a semiconductor memory device 100 including a conventional ECC circuit 120. The semiconductor memory device 100 includes a memory core 110, the ECC circuit 120, and a host interface and logic unit 130.
The memory core 110 is a block including a memory cell array for storing data. The ECC circuit 120 includes an ECC encoder 121 and an ECC decoder 123. The host interface and logic unit 130 performs data interface between a host 200 (e.g., a controller in a mobile device) and the memory core 110. The host interface and logic unit 130 can transmit and receive d-bit parallel data (where “d” is 2 or an integer greater than 2) to and from the host 200.
The ECC encoder 121 receives k-bit data through the host interface and logic unit 130, generates (n−k)-bit syndrome data using the received k-bit data, and adds the (n−k)-bit syndrome data to the k-bit data. Accordingly, n-bit data (which may be referred to as an ECC word) comprised of the received k-bit data and the (n−k)-bit syndrome data is input into the memory core 110.
When data stored in the memory core 110 is output, an ECC word, which is comprised of k-bit data and (n−k)-bit syndrome data, is read from the memory core 110. The ECC decoder 123 divides the ECC word by predetermined pattern data, generates syndrome data, and determines existence or non-existence of an error using the syndrome data. When an error is determined to exist, the ECC decoder 123 detects a position of the error, that is, a position of a bit having the error, and corrects the error bit. The correction of the error bit may be carried out by an error corrector included in a unit, e.g., the host interface and logic unit 130 within the semiconductor memory device 100 or by the host 200.
FIG. 2 is a timing diagram illustrating conventional error correction. The conventional error correction includes data read/syndrome calculation in a period Tt between times T0 and T1, coefficient calculation in a period Tcoeff between times T1 and T2, and error position calculation in a period Tcse between times T2 and T3.
During the data read/syndrome calculation, an ECC word (i.e., information data and syndrome data) is read from a memory cell array and partial syndromes S0 through S2n−1 are calculated. The data read/syndrome calculation requires a predetermined read time Tt. During the coefficient calculation, coefficients σ0 through σn necessary for producing an error position equation are calculated and a predetermined coefficient calculation time Tcoeff is required. During the error position calculation, the error position equation is solved to obtain a solution so that an error position is detected. The error position calculation requires a predetermined error position calculation time Tcse. Accordingly, an error correction cycle (or an ECC cycle) corresponds to the sum of the time periods Tt, Tcoeff, and Tcse, and is almost always constant regardless of the number of error bits.
Known circuits and methods for multi-bit ECC have many disadvantages. For example, a conventional ECC decoder is designed and implemented based on a maximum number of correctable error bits. A conventional multi-bit ECC decoder requires more processing time than single bit ECC decoder. Moreover, the error correction cycle is directly related to data access time (the time for a host to read data from a semiconductor memory device). As a consequence, conventional multi-bit ECC circuits and methods may result in significantly slower data read times from memory. Faster multi-bit ECC circuits and methods are needed.